1. Field of the Invention
The present invention relates to a semiconductor device whose gate and source electrodes have trench structures, and a method of manufacturing the same.
2. Description of the Background Art
In power semiconductor devices, a large number of unit cells having the same structure are connected in parallel in order to achieve characteristics such as high-speed switching, reduction of the resistance in conducting state caused by high current density (hereinafter also referred to as “on-state resistance”), and high breakdown withstand voltage. In the development of power semiconductor devices, miniaturization is now in progress for purposes such as the reduction of on-state resistance.
Particularly, miniaturization techniques for low-voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are being developed, for pattern miniaturization is directly connected to performance. Devices according to leading-edge miniaturization techniques are adopting double trench cell structure in which not only gate electrode contacts but also source electrode contacts have trench structures (for example, see Japanese Patent Application Laid-Open Nos. 2007-35841, 2007-311557, and 2003-318396, hereinafter respectively referred to as Patent Documents 1 to 3).
Gate electrodes and source electrodes in the double trench cell structure are formed by forming an electrode film to fill a trench by sputtering, for example. It is difficult to fill a trench with an electrode film formed by sputtering, so that voids are likely to form inside the electrode and increase the electrode resistance. Also, the electrode tends to rise up over the trench to form irregularities on the electrode surface, leading to increased connection resistance with external interconnections like wire bonding.
For example, Patent Document 3 mentioned above discloses a technique related to the surface configuration of electrodes. In the technique disclosed in Patent Document 3, tungsten is buried as a plug in a contact hole corresponding to a trench by, e.g. Chemical Vapor Deposition (CVD), and then a source electrode is formed thereon, so that the surface of the source electrode is formed flat.
As described above, power MOSFETs are now in progress toward miniaturization. The progress toward miniaturization leads to increased gate resistance and increased delay in switching due to increased time constant CR. Also, the increased gate resistance causes variations in switching speed in a single chip, leading to non-uniform operations.
Furthermore, since a large number of trenches, about twice or more times those in conventional ones, are packed in fine areas, stresses occurring in trench regions cause problems in large-current and high-temperature operating power devices. Excessive stresses will cause crystal defects and increased leakage, and it is therefore necessary to alleviate stresses as much as possible.
Patent Documents 1 to 3 mentioned above disclose no technique for solving these problems.